/*
 * file: nmos.v
 * test for ??mos gates: (r)nmos, (r)pmos
 * I assume tha a workinkg nmos implies a working pmos.
 */

module cucu;

  reg control, data;
  wire out, in = data;

  nmos nm (out, in, control);

  reg [1:0] acontrol, adata;
  wire [1:0]  aout, ain;

  nmos anm [1:0] (aout, ain, acontrol); 

  assign (weak1, weak0)  ain = adata;

  task do_control_sgate;
  begin
    control = 0;
    $strobe("%v \t%b\t%b", out, control, in);
    #1;
    control = 'b1;
    $strobe("%v \t%b\t%b", out, control, in);
    #1;
    control = 'bx;
    $strobe("%v \t%b\t%b", out, control, in);
    #1;
    control = 'bz;
    $strobe("%v \t%b\t%b", out, control, in);
    #1;
  end
  endtask
  
  task do_single_gate;
  begin
    $display("single gate:");
    $display("out\t\t\tcontrol\tin\t\t\n-----------------------------------------");
    data = 0;
    do_control_sgate();
    data = 1;
    do_control_sgate();
    data = 'bx;
    do_control_sgate();
    data = 'bz;
    do_control_sgate();
  end
  endtask


  task do_control_agate;
  begin
    acontrol = 0;
    $strobe("%v  \t%b\t\t%b", aout, acontrol, ain);
    #1;
    acontrol = 'b11;
    $strobe("%v  \t%b\t\t%b", aout, acontrol, ain);
    #1;
    acontrol = 'bxx;
    $strobe("%v  \t%b\t\t%b", aout, acontrol, ain);
    #1;
    acontrol = 'bzz;
    $strobe("%v  \t%b\t\t%b", aout, acontrol, ain);
    #1;
  end
  endtask
  
  task do_gate_array;
  begin
    $display("\ngate array");
    $display("aout\t\t\t\t\tacontrol\tain\t\t\n--------------------------------------------------------------");
    adata = 0;
    do_control_agate();
    adata = 'b11;
    do_control_agate();
    adata = 'bxx;
    do_control_agate();
    adata = 'bzz;
    do_control_agate();
  end
  endtask


  initial begin
    do_single_gate();
    do_gate_array();
  end
endmodule

